intel 13th gen DDR5 timing "cheat sheet" rev0.2
Added 2023-03-29 17:03:09 +0000 UTCThis is a list of the majority of DDR5 timings that actually have registers on intel CPUs. (there's a bunch of timings in mobo BIOSs that don't actually exist on intel CPUs for example: tWTR_S/L ). Along with my understanding of each timing. So there might be mistakes because I don't design memory controllers or memory chips.
Comments
Not a chance. The memory controllers are too different. BZ's already pointed out a couple of settings that work on Intel but do nothing for Zen4 in a video not too long ago.
tibbish
2023-03-29 19:20:00 +0000 UTCSweet, does it apply to AM5 also?
Damian Toczek
2023-03-29 18:52:23 +0000 UTC
